The need for higher speed systems is increasing, particularly with the development of more sophisticated networks, multimedia applications and high speed communications. The needs are such that today, switches accepting speeds of 100 gigabits will be more and more in demand. However, a problem arises from the fact that the speed of a switch is strongly dependent on the actual technology that is used.
Therefore, for a given state of technology, it would appear difficult to achieve enhancement of switches that are known. There is therefore a need in the art for aggregating basic switching modules in such a manner that preserves the internal capabilities and efficiency of the module. Particularly, it is preferable that the aggregated switching structure does not require input or output ports, thus decreasing the number of ports that remain for a user. Additionally, it is preferable that the aggregate switching structure remains in a single stage.
Another problem arises from the circumstances that a user's premises are often equipped with line attachments that are fixed and determined for a relatively long period of time, as investments made in telecommunications equipment are often substantial. Therefore, although there is a strong need for higher speed switching systems, there is a desire for utilizing investments that have already been made, and thus for permitting a wide range of attachments.
As is known, speed expansion from input lines having a speed of 2 gigabits/second to input lines having a speed of 4 gigabits/second may be achieved by combining two switching modules. When received by an adapter, a packet may be split into two portions. A first portion containing a packet header with control information therein, for example routing or priority information, is sent to a master module while, at the same time, a second portion containing data is sent to a slave module. When the master module receives the packet header, validity of the packet is verified. If the packet is valid, the master module sends the control information to the slave module using a speed expansion bus. The slave module receives the control information within a packet cycle which, in one example, is 128 nanoseconds (hereinafter referred to as “ns”) with packets of 64 bytes. Subsequently, the portion of the packet respectively received in the master and slave switching modules is stored in a shared buffer.
Similarly, when control logic associated with a switch sends a packet to an output adapter, the master module reads the shared buffer and a packet address is sent from the master module to the slave module using the speed expansion bus. The packet address is received within a packet cycle by the slave module which then reads the shared buffer and both master and slave modules start to send respective portions of the packet at substantially the same time within the packet cycle.
Therefore, as is described hereinabove, it is possible to use two switching modules in association with a data transmission line, the speed of which has doubled, insofar as it is possible for the master module to send control information within a packet cycle. However, assuming that data speed expansion is such that a plurality of switching modules, for example eight (8) modules, are needed to accommodate a given data speed, it would no longer be possible to send the control information to all switching modules linked in series before data are received by each module.
Moreover, it would not be possible at relatively higher speeds to use a multi-drop configuration wherein the master module drives a single bus, or to implement a bus inside the master module because of the resulting large number of input/output ports in the module.
It is believed, therefore, that a multi-module switching system which provides the many advantages taught herein would obviate many of the problems and limitations described hereinabove, and would constitute a significant advancement in the art.